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l q qt1081 8-k ey qt ouch ? s ensor ic this datasheet is applicable to all revision 1 chips at a glance number of keys: 1 to 8 technology: patented spread-spectrum charge-transfer (one-per-key mode) key outline sizes: 5mm x 5mm or larger (panel thickness dependent); widely different sizes and shapes possible key spacings: 6mm or wider, center to center (panel thickness, human factors dependent) electrode design: single solid or ring shaped electrodes; wide variety of possible layouts layers required: one layer substrate; electrodes and components can be on same side substrates: fr-4, low cost cem-1 or fr-2 pcb materials; polyamide fpcb; pet films, glass electrode materials: copper, silver, carbon, ito, orgacon ? ink (virtually anything electrically conductive) panel materials: plastic, glass, composites, painted surfaces (low particle density metallic paints possible) adjacent metal: compatible with grounded metal immediately next to keys panel thickness: up to 50mm glass, 20mm plastic (key size dependent) key sensitivity: settable via change in reference capacitor (cs) value outputs: parallel discrete output, one-per-key, active-high moisture tolerance: good power: 2.8v ~ 5.0v, <15a (8 keys at 2.8v, 340ms low power mode). package: 32-pin 5 x 5mm qfn rohs compliant signal processing: self-calibration, auto drift compensation, noise filtering, patented adjacent key suppression tm applications: portable devices, domestic appliances and a/v gear, pc peripherals, office equipment patents: aks? (patented adjacent key suppression) qtouch? (patented charge-transfer method) ? orgacon is a registered trademark of agfa-gevaert n.v l q copyright ? 2006-2007 qrg ltd qt1081_1r0.04_0307 the qt1081 is an improved, lower cost, simplified circuit version of the popular qt1080 sensor ic. the qt1081 is designed for low cost appliance, mobile, and consumer electronics applications. qtouch? technology is a type of patented charge-transfer sensing method well known for its robust, stable, emc-resistant characteristics. it is the only all-digital capacitive sensing technology in the market today. this technology has over a decade of applications experience spanning thousands of designs. qtouch circuits are renowned for simplicity, reliability, ease of design, and cost effectiveness. qtouch? sensors employ a single reference capacitor tied to two pins of the chip for each sensing key; a signal trace leads from one of the pins to the sensing electrode which forms the key. the sensing electrode can be a simple solid shape such as a rectangle or circle. an led can be placed near or inside the solid circle for illumination. the key electrodes can be designed into a conventional printed circuit board (pcb) or flexible printed circuit board (fpcb) as a copper pattern, or as printed conductive ink. the qt1081 is also compatible with clear films to make simple button-style touch screens over lcd displays. QT1081-ISG -40 o c to +85 o c 32-qfn t a available option 28 2 /rst 3 vdd 4 osc 5 n/c 6 sns0 7 sns0k 8 sns1 23 sync/lp 24 detect 22 vss 21 sns7k 20 sns7 19 sns6k 18 sns6 17 sns5k 9 sn1k 10 sns2 11 sns2k 12 sns3 13 sns3k 14 sns4 15 sns4k 16 sns5 31 out_6 30 out_5 29 out_4 out_3 27 out_2 26 out_1 25 out_0 1 ss qt1081 32-qfn 32 out_7
9 2.8 mod_0, mod_1 inputs ............................... 9 2.7 aks? function pins ................................. 8 2.6 sync/lp pin ...................................... 8 2.5 detect pin ...................................... 8 2.4 binary coded output mode ............................ 8 2.3 one-per-key output mode ............................. 8 2.2 option resistors .................................... 8 2.1 start-up time ...................................... 8 2 device operation .................................... 5 1.3 wiring ........................................... 4 1.2.12 simplified mode .................................. 4 1.2.11 outputs ....................................... 3 1.2.10 adjacent key suppression (aks?) ...................... 3 1.2.9 low power (lp) mode ............................... 3 1.2.8 sync mode ..................................... 3 1.2.7 spread-spectrum operation ............................ 3 1.2.6 detection integrator confirmation ........................ 3 1.2.5 drift compensation ................................. 3 1.2.4 autorecalibration .................................. 3 1.2.3 self-calibration ................................... 3 1.2.2 burst operation ................................... 3 1.2.1 introduction ..................................... 3 1.2 parameters ....................................... 3 1.1 differences with qt1080 .............................. 3 1 overview ........................................... 18 5.2 numbering convention .............................. 18 5.1 changes ........................................ 18 5 datasheet control ................................... 17 4.10 moisture sensitivity level (msl) ....................... 17 4.9 part marking ..................................... 16 4.8 mechanical - 32-qfn package ......................... 15 4.7 lp mode typical response times ...................... 14 4.6 average idd curves ................................ 13 4.5 signal processing ................................. 12 4.4 dc specifications .................................. 12 4.3 ac specifications .................................. 12 4.2 recommended operating conditions .................... 12 4.1 absolute maximum specifications ....................... 12 4 specifications ...................................... 11 3.5 pcb layout and construction .......................... 11 3.4 power supply ..................................... 11 3.3 cs sample capacitors - sensitivity ...................... 11 3.2 spread-spectrum circuit ............................. 11 3.1 oscillator frequency ................................ 11 3 design notes ....................................... 10 2.11 unused keys .................................... 10 2.10 simplified mode .................................. 9 2.9 fast detect mode ................................... contents l q 2 qt1081_1r0.04_0307
1 overvie w 1.1 differences with qt1080 the qt1081 is a general replacement device for the highly popular qt1080. it has all of the same features as the older device but differs in the following ways: ? rs resistors on each channel eliminated ? up to 4x more sensitive for a given value of cs ? shorter burst lengths, less power for a given value of cs ? ?burst b? only mode for lower key counts with less power the qt1081 should be used over the qt1080 for new designs due to a simpler circuit, lower power and lower cost. 1.2 parameters 1.2.1 introduction the qt1081 is an easy to use, eight-touch-key sensor ic based on quantum?s patented charge-transfer principles for robust operation and ease of design. this device has many advanced features which provide for reliable, trouble-free operation over the life of the product. 1.2.2 burst operation the device operates in ?burst mode?. each key is acquired using a burst of charge-transfer sensing pulses whose count varies depending on the value of the reference capacitor cs and the load capacitance cx. in lp mode, the device sleeps in an ultra-low current state between bursts to conserve power. the keys? signals are acquired using two successive bursts of pulses: burst a: keys 0, 1, 4, 5 burst b: keys 2, 3, 6, 7 bursts always operate in a-b sequence. 1.2.3 self-calibration on power-up, all eight keys are self- calibrated within 300 milliseconds (typical) to provide reliable operation under almost any conditions. 1.2.4 autorecalibration the device can time out and recalibrate each key independently after a fixed interval of continuous touch detection, so that the keys can never become ?stuck on? due to foreign objects or other sudden influences. after recalibration the key will continue to function normally. the delay is selectable to be either 10s, 60s, or infinite (disabled). the device also autorecalibrates a key when its signal reflects a sufficient decrease in capacitance. in this case the device recalibrates after ~2 seconds so as to recover normal operation quickly. 1.2.5 drift compensation drift compensation operates to correct the reference level of each key slowly but automatically over time, to suppress false detections caused by changes in temperature, humidity, dirt and other environmental effects. the drift compensation is asymmetric; in the increasing capacitive load direction the device drifts more slowly than in the decreasing direction. in the increasing direction, the rate of compensation is one count of signal per 2 seconds; in the opposing direction, it is one count every 500ms. 1.2.6 detection integrator confirmation detection integrator (di) confirmation reduces the effects of noise on the qt1081. the ?detect integrator? mechanism requires consecutive detections over a number of measurement bursts for a touch to be confirmed and indicated on the outputs. in a like manner, the end of a touch (loss of signal) has to be confirmed over a number of measurement bursts. this process acts as a type of ?debounce? against noise. a per-key counter is incremented each time the key has exceeded its threshold and stayed there for a number of measurement bursts. when this counter reaches a preset limit the key is finally declared to be touched. for example, if the limit value is six, then the device has to exceed its threshold and stay there for six measurement bursts in succession without going below the threshold level, before the key is declared to be touched. if on any measurement burst the signal is not seen to exceed the threshold level, the counter is cleared and the process has to start from the beginning. in normal operation, both the start and end of a touch must be confirmed for six measurement bursts. in a special ?fast detect? mode (available via jumper resistors), confirmation of the start of a touch requires only two sequential detections, but confirmation of the end of a touch is still six bursts. fast detect is only available when aks is disabled. 1.2.7 spread-spectrum operation the bursts operate over a spread of frequencies, so that external fields will have minimal effect on key operation and emissions are very weak. spread-spectrum operation works with the di mechanism to dramatically reduce the probability of false detection due to noise. 1.2.8 sync mode the qt1081 features a sync mode to allow the device to slave to an external signal source, such as a mains signal (50/60hz), to limit interference effects. this is performed using the sync/lp pin. sync mode operates by triggering two sequential acquire bursts, in sequence a-b from the sync signal. thus, each sync pulse causes all eight keys to be acquired. 1.2.9 low power (lp) mode the device features an lp mode for microamp levels of current drain with a slower response time, to allow use in battery operated devices. on touch detection, the device automatically reverts to its normal mode and asserts the detect pin active to wake up a host controller. the device remains in normal, full acquire speed mode until requested to return to lp mode. when four or fewer keys are required, current drain in lp mode can be further reduced by choosing appropriate channels on the qt1081. 1.2.10 adjacent key suppression (aks?) aks? is a quantum-patented feature that can be enabled via resistor strap option. aks works to prevent multiple keys from responding to a single touch, a common complaint about capacitive touch panels. this can happen with closely spaced keys, or with control surfaces that have water films on them. aks operates by comparing signal strengths from keys within a group of keys to suppress touch detections from those that have a weaker signal change than the dominant one. l q 3 qt1081_1r0.04_0307
the qt1081 has two different aks groupings of keys, selectable via option resistors. these groupings are: y aks operates in two groups of four keys. y aks operates over all eight keys. these two modes allow the designer to provide aks while also providing for shift or function operations. if aks is disabled, all keys can operate simultaneously. 1.2.11 outputs there are two output modes: one-per-key, and binary coded. one - per - key output: in this mode there is one output pin per key. this mode has two output drive options, push-pull and open-drain. the outputs can also be made either active-high or active-low. these options are set via external configuration resistors. binary coded output: in this mode, three output lines encode for one possible key in detect. if more than one key is detecting, only the first one touched will be indicated. 1.2.12 simplified mode to reduce the need for option resistors, the simplified operating mode places the part into fixed settings with only the aks feature being selectable. lp mode is also possible in this configuration. simplified mode is suitable for most applications. l q 4 qt1081_1r0.04_0307
1.3 wiring table 1.1 pinlist open out 7 o/od out_7 32 open out 6 o/od out_6 31 open out 5 o/od out_5 30 open out 4 o/od out_4 29 open in binary coded mode, these pins are clamped internally to vss out 3 o/od out_3 28 open also, binary coded output 2 out 2 o/od out_2 27 open also, binary coded output 1 out 1 o/od out_1 26 open also, binary coded output 0 out 0 o/od out_0 25 open active = any key in detect detect status o/od detect 24 vdd or vss rising edge sync or lp pulse sync in or lp in i sync/lp ? 23 - 0v ground pwr vss 22 open to cs7 + key sense pin i/o sn7k 21 open or mode resistor ? or option resistor* to cs7 and/or mode resistor ? or option resistor* sense pin and mode or option select i/o sns7 20 open or mode resistor ? to cs6 + key and/or mode resistor ? sense pin and mode select i/o sns6k 19 open or option resistor* to cs6 and/or option resistor* sense pin and option select i/o sns6 18 open to cs5 + key sense pin i/o sns5k 17 open or option resistor* to cs5 and/or option resistor* sense pin and option select i/o sns5 16 open to cs4 + key sense pin i/o sns4k 15 open or option resistor* to cs4 and/or option resistor* sense pin and option select i/o sns4 14 open to cs3 + key sense pin i/o sns3k 13 open or option resistor* to cs3 and/or option resistor* sense pin and option select i/o sns3 12 open to cs2 + key sense pin i/o sns2k 11 open or option resistor* to cs2 and/or option resistor* sense pin and option select i/o sns2 10 open to cs1 + key sense pin i/o sns1k 9 open or option resistor* to cs1 and/or option resistor* sense pin and option select i/o sns1 8 open to cs0 + key sense pin i/o sns0k 7 option resistor to cs0 and/or option resistor sense pin and option select i/o sns0 6 - leave open - - n/c 5 - resistor to vdd and optional spread spectrum rc network oscillator i osc 4 - +2.8 ~ +5.0v power pwr vdd 3 vdd active low reset reset input i /rst 2 100k resistor to vss spread spectrum drive spread spectrum od ss 1 if unused notes function type name 32-qfn pin pin type i cmos input only i/o cmos i/o o cmos push-pull output od cmos open drain output o/od cmos push pull or open-drain output (option selected) pwr power / ground notes ? mode resistor is required only in simplified mode (see figure 1.2) * option resistor is required only in full options mode (see figure 1.1) ? pin is either sync or lp depending on options selected (functions sl_0, sl_1, see figure 1.1) l q 5 qt1081_1r0.04_0307
figure 1.1 connection diagram - full options table 1.2 aks / fast-detect options table 1.3 max on-duration table 1.4 polarity and output table 1.5 sync/lp function l q 6 qt1081_1r0.04_0307 sns3 sns3k sns4 sns4k sns5 sns5k sns6 sns6k sns7 sns7k vss detect sync/lp sns2k sns2 /rst out_7 out_6 out_5 out_4 out_3 out_2 out_1 out_0 10k 1nf 10k 10k 10k 10k 1nf 1nf 1nf key 2 10k 1nf out_1 out_0 detect out sync or lp in out_2 out_3 out_4 out_5 out_6 out_7 qt1081 32-qfn 1nf 1m 1m 1m 1m 1m vdd / vss vdd / vss vdd / vss vdd / vss vdd / vss 1m vdd / vss pol mod_1 out_d sl_0 sl_1 mod_0 out_0 vdd vunreg *4.7uf *4.7uf *100nf +2.8 ~ +5v voltage reg vdd 12 13 15 16 18 19 20 21 24 23 11 10 3 2 32 31 30 29 28 27 26 25 22 key 3 key 4 key 5 key 6 key 7 r sns3 c s3 r sns4 r sns5 r sns6 r sns7 c s4 c s7 c s2 r sns2 sns1k sns1 10k 1nf 1m vdd / vss aks_1 9 8 key 1 r sns1 c s1 sns0k sns0 10k 1nf 1m vdd / vss aks_0 7 6 key 0 r sns0 c s0 vdd range rb1 rb2 3.6 ~ 5v 2.8 ~ 3.59v 12k 22k 15k 27k recommended rb1, rb2 values osc ss 4 1 rb1 rb2 vdd c ss the required value of spread-spectrum capacitor css will vary according to the lengths of the acquire bursts, see section 3.2. a typical value of is 100nf. css binary coded output mode 14 keep these parts close to the ic keep these parts close to the ic * note: one bypass capacitor to be tightly wired between vdd and vss. follow manufacturer?s recommendations for input and output capacitors. off on, global vdd vdd off on, in 2 groups vss vdd enabled off vdd vss off off vss vss fast-detect aks mode aks_0 aks_1 (reserved) vdd vdd infinite (disabled) vss vdd 60 seconds (nom) to recalibrate vdd vss 10 seconds (nom) to recalibrate vss vss max on-duration mode mod_0 mod_1 one-per-key, active low, push-pull vdd vdd one-per-key, active high, push-pull vss vdd one-per-key, active low, open-drain vdd vss binary coded, active high, push-pull vss vss out_n, detect pin mode pol out_d lp mode: 340ms nom response time vdd vdd lp mode: 180ms nom response time vss vdd lp mode: 100ms nom response time vdd vss sync vss vss sync/lp pin mode sl_0 sl_1
figure 1.2 connection diagram - simplified mode table 1.6 aks resistor options table 1.7 functions in simplified mode active high on any detect detect pin 60 seconds (nom) max on-duration delay 180ms nom lp function; sync not available sync/lp pin one-per-key outputs, push-pull, active high output drive, polarity parameter function l q 7 qt1081_1r0.04_0307 sns3 sns3k sns4 sns4k sns5 sns5k sns6 sns6k sns7 sns7k vss detect sync/lp sns2k sns2 sns1k sns1 sns0k sns0 osc /rst out_7 out_6 out_5 out_4 out_3 out_2 out_1 out_0 ss 12 13 15 16 17 18 19 20 21 24 23 11 10 9 8 7 6 4 3 2 1 32 31 30 29 28 27 26 25 1 0 k 1 n f 10k 10k 10k 10k 1nf 1nf 1nf 10k 10k 10k 1nf 1nf 1nf rb1 rb2 vdd c ss out_1 out_0 detect out lp in out_2 out_3 out_4 out_5 out_6 out_7 1nf 1m vdd / vss 1m aks_0 smr out_0 22 vdd vunreg *4.7uf *4.7uf +2.8 ~ +5v voltage reg vdd *100nf key 3 key 4 key 5 key 6 key 7 key 2 key 1 key 0 c s3 r sns4 r sns5 r sns6 r sns7 c s4 c s5 c s6 c s7 c s2 r sns2 r sns1 r sns0 c s1 c s0 qt1081 32-qfn vdd range rb1 rb2 2.8 ~ 3.59v 12k 22k 3.6 ~ 5v 15k 27k recommended rb1, rb2 values the required value of spread-spectrum capacitor will vary according to the lengths of the acquire bursts, see section 3.2. a typical value of is 100nf. css css keep these parts close to the ic keep these parts close to the ic * note: one bypass capacitor to be tightly wired between vdd and vss. follow manufacturer?s recommendations for input and output capacitors. r sns3 off on, global vdd enabled off vss fast-detect aks mode aks_0
2 device operation 2.1 start-up time after a reset or power-up event, the device requires 300ms to initialize, calibrate, and start operating normally. keys will work properly once all keys have been calibrated after reset. 2.2 option resistors the option resistors are read on power-up only; it is not possible to change the operating mode of the device once it has powered up. there are two primary option mode configurations: full, and simplified. full options mode: eight 1m option resistors are required as shown in figure 1.1. all eight resistors are mandatory. simplified mode: a 1m resistor should be connected from sns6k to sns7. in simplified mode, only one additional 1m option resistor is required for the aks feature (figure 1.2). note that the presence and connection of option resistors will affect the required values of cs; this effect will be especially noticeable if the cs values are under 22nf. cs values should be adjusted for optimal sensitivity after the option resistors are connected. 2.3 one-per-key output mode one-per-key output mode is selected via option resistors, as shown in table 1.4. in this mode, there is one output for each key; each is active when a touch is confirmed on the corresponding electrode. unused out pins should be left open. if aks is off, it is possible for all out pins to be active at the same time. circuit of figure 1.1: out polarity and drive are governed by the resistor connections to vdd or vss according to table 1.4. the drive can be either push-pull or open-drain, active low or high. circuit of figure 1.2: in this simplified circuit, the out pins are active high, push-pull only. 2.4 binary coded output mode this mode is useful to reduce the number of connections to a host controller, at the expense of only being able to report one active key at a time. note that in global aks mode (section 2.7), only one key can report active at a time anyway. binary coded mode is selected via option resistors, as shown in table 1.4. in this mode, a key detection is registered as a binary code on pins out_2, out_1 and out_0, with possible values from 000 to 111. in practice, four lines are required to read the code, unless key 0 is not implemented; the output code 000 can mean either ?nothing detecting? or ?key 0 is detecting?. the fourth required line (if all eight keys are implemented) is the detect signal, which is active-high when any key is active. the first key touched always wins and shows its output. keys that come afterwards are hidden until the currently reported key has stopped detecting, in which case the code will change to a latent key. circuit of figure 1.1: out polarity and drive can only be push-pull and active high. circuit of figure 1.2: binary coded not available. 2.5 detect pin detect represents the functional logical-or of all eight keys. detect can be used to wake up a battery-operated product upon human touch. detect is also required to indicate to a host when the binary coded output pins (in that mode) are showing an active key. while detect is active, the binary coded outputs should be read at least twice along with detect to make sure that the code was not transitioning between states, to prevent a false reading. the output polarity and drive of detect are governed according to table 1.4. 2.6 sync/lp pin when full options are in use, the sync/lp pin function is selected according to the sl_0 and sl_1 resistor connections as given in table 1.5. when the qt1081 is in sync mode the pin acts as a sync input; when the qt1081 is in lp mode the pin acts as an lp input. when simplified options are in use, the qt1081 is always in lp mode and the sync/lp pin acts as an lp input. sync mode: sync mode allows the designer to synchronize acquire bursts to an external signal source, such as mains frequency (50/60 hz) to suppress interference. it can also be used to synchronize two qt parts which operate near each other, so that only one part generates acquire bursts at a time and hence they do not cross-interfere. the sync input of the qt1081 is positive edge triggered. following each rising edge the qt1081 will generate a pair of acquire bursts in a-b sequence; this operation is shown in figure 2.1. figure 2.1 acquire bursts in a-b sequence sync burst a burst b if the sync input does not change level for ~150ms, the qt1081 will free-run, generating a continuous stream of acquire bursts a-b-a-b-a-... . while the qt1081 is in free-run operation, a rising edge on the sync input will return the qt1081 to synchronised operation. note that the sync input must remain at one level (high or low) for >150s to guarantee that the qt1081 will recognise that level. low power lp mode: lp mode allows the device to be switched between full speed operation (20ms typical response time and normal power consumption), and low power operation (low average power consumption but an increased maximum response time) according to the needs of the application. there are three maximum response time settings for low power operation: 100ms, 180ms, and 340ms nominal; the response time setting is determined by option resistors sl_1 and sl_0; see table 1.5. slower response times result in a lower average power drain. l q 8 qt1081_1r0.04_0307
operation in low power mode is governed by the state of the lp input and whether at least one key has a confirmed touch. if the lp input is at a constant low level, then the qt1081 will remain in full speed operation (20ms typical response time and normal power consumption), as in figure 2.2. figure 2.2 full speed operation touch lp pin bursts full speed operation if the lp input is at a constant high level, then the qt1081 will enter low power operation whenever it is not detecting a touch. it will switch automatically to full speed operation while there is a touch, and revert to low power operation at the end of the touch. this is shown in figure 2.3. figure 2.3 low power/full speed operation e touch lp pin bursts full speed low power low power while there is no touch, if the lp input is driven high then low, the qt1081 will enter low power operation, as described above, and remain in low power operation when lp is taken low. when there is a touch the qt1081 will switch automatically to full speed operation. at the end of the touch the choice of operation depends on the state of the lp input. this is shown in figures 2.4 and 2.5 - the first with the lp pin being low at the end of the touch, and the second with the lp pin being high at the end of the touch. figure 2.4 lp pin low at end of touch e touch lp pin bursts full speed low powe r figure 2.5 lp pin high at end of touch e touch lp pin bursts full speed low power low power note that the lp input must remain at one level (high or low) for >150s to guarantee that the qt1081 will recognise that level. optimization of lp mode: for the lowest possible power consumption when up to four keys are required, all keys should be connected to qt1081 channels that are measured during acquire burst b (i.e. k2, k3, k6 and k7). if this is done the qt1081 automatically selects optimized lp operation, which gives a significantly lower power consumption than would be achieved if the burst a channels were used. optimized lp operation is identical to the standard lp operation in all other ways; it is controlled as described above. 2.7 aks? function pins the qt1081 features an adjacent key suppression (aks) function with two modes. option resistors act to set this feature according to tables 1.2 and 1.6. aks can also be disabled, allowing any combination of keys to become active at the same time. when operating, the modes are: global: aks functions operates across all eight keys. this means that only one key can be active at any one time. groups: aks functions among two groups of four keys: 0-1-4-5 and 2-3-6-7. this means that up to two keys can be active at any one time. in group mode, keys in one group have no aks interaction with keys in the other group. note that in fast detect mode, aks can only be off. 2.8 mod_0, mod_1 inputs in full option mode, mod_0 and mod_1 resistors are used to set the ?max on-duration? recalibration timeouts. if a key becomes stuck on for a lengthy duration of time, this feature will cause an automatic recalibration event of that specific key once the specified on-time has been exceeded. settings of 10s, 60s, and infinite are available. the max on-duration feature operates on a key-by-key basis; when one key is stuck on, its recalibration has no effect on other keys. the logic combination on the mod option pins sets the timeout delay (see table 1.3). simplified mode mod timing: in simplified mode, the max on-duration is fixed at 60 seconds. 2.9 fast detect mode l q 9 qt1081_1r0.04_0307
in many applications, it is desirable to sense touch at high speed. examples include scrolling ?slider? strips or ?off? buttons. it is possible to place the device into a ?fast detect? mode that usually requires under 10ms to respond. this is accomplished internally by setting the detect integrator to only two counts, i.e. only two successive detections are required to detect touch. in lp mode, ?fast? detection will not speed up the initial delay (which could be up to 340ms nominal depending on the option setting). however, once a key is detected the device is forced back into normal speed mode. it will remain in this faster mode until requested to return to lp mode. when used in a ?slider? application, it is normally desirable to run the keys without aks. in both normal and ?fast? modes, the time required to process a key release is the same. it takes six sequential confirmations of nondetection to turn a key off. fast detect mode can be enabled as shown in tables 1.2 and 1.6. 2.10 simplified mode a simplified operating mode which does not require the majority of option resistors is available. this mode is set by connecting a resistor labelled smr between pins sns6k and sns7 (see figure 1.2). in this mode there is only one option possible - aks enable or disable. when aks is disabled, fast detect mode is enabled; when aks is enabled, fast detect mode is off. aks in this mode is global only (i.e. operates across all functioning keys). the other option features are fixed as follows: out_n, detect pins: push-pull, active high, one-per-key outputs sync/lp function: lp mode, ~180ms response time max on-duration: 60 seconds see tables 1.6 and 1.7. 2.11 unused keys unused keys should be disabled by removing the corresponding cs, rs, and rsns components and connecting sns pins as shown in the ?unused? column of table 1.1. unused keys are ignored and do not factor into the aks function (section 2.7). l q 10 qt1081_1r0.04_0307
3 design notes 3.1 oscillator frequency the qt1081?s internal oscillator runs from an external resistor network connected to the osc and ss pins, as shown in figures 1.1 and 1.2, to achieve spread-spectrum operation. if spread-spectrum mode is not required, the osc pin should be connected to vdd with an 18k ? one percent resistor. under different vdd voltage conditions the resistor network (or the solitary 18k ? resistor) might require minor adjustment to obtain the specified burst center frequency. the network should be adjusted slightly so that the positive pulses on any key are approximately 2.67s wide in the ?solitary 18k ? resistor? mode, or 2.87s wide at the beginning of a burst with the recommended spread-spectrum circuit (see next section). in practice, the pulse width has little effect on circuit performance if it varies in the range of 2s to 3.3s. the only effects seen will be proportional variations in max on-duration and non-lp mode response times. 3.2 spread-spectrum circuit the qt1081 offers the ability to spectrally spread its frequency of operation to heavily reduce susceptibility to external noise sources and to limit rf emissions. the ss pin is used to modulate an external passive rc network that modulates the osc pin. osc is the main oscillator current input. the circuit is shown in both figures 1.1 and 1.2. the resistors rb1 and rb2 should be changed depending on vdd. as shown in figures 1.1 and 1.2, two sets of values are recommended for these resistors depending on vdd. the power curves in section 4.6 also show the effect of these resistors. the circuit can be eliminated, if it is not desired, by using an 18k ? resistor from osc to vdd to drive the oscillator, and connecting ss to vss with a 100k ? resistor. the spread-spectrum rc network will need to be adjusted according to the burst lengths. the sawtooth waveform observed on ss should reach a crest height as follows: vdd >= 3.6v: 17 percent of vdd vdd < 3.6v: 20 percent of vdd the css capacitor connected to the ss pin (figures 1.1 and 1.2) should be adjusted so that the waveform approximates the above amplitude, 10 percent, during normal operation in the target circuit. where the bursts are of differing lengths, the adjustment should be done for the longer burst. if this is done, the circuit will give a spectral modulation of 12-15 percent. use of the spread-spectrum facility has the following effect on idd: ? full speed operation: idd changes within 10 percent. ? idd increases by up to 15 percent. in both cases the exact value depends on the precise circuit component values and timing. vdd variations can shift the center frequency and spread slightly. 3.3 cs sample capacitors - sensitivity the cs sample capacitors accumulate the charge from the key electrodes and determine sensitivity. higher values of cs make the corresponding sensing channel more sensitive. the values of cs can differ for each channel, permitting differences in sensitivity from key to key or to balance unequal sensitivities. unequal sensitivities can occur due to key size and placement differences and stray wiring capacitances. more stray capacitance on a sense trace will desensitize the corresponding key; increasing the cs for that key will compensate for the loss of sensitivity. the cs capacitors can be virtually any plastic film or low to medium-k ceramic capacitor. the normal cs range is 1nf to 50nf depending on the sensitivity required; larger values of cs require better quality to ensure reliable sensing. in certain circumstances the normal cs range may be exceeded, hence the different values in section 4.2. acceptable capacitor types for most uses include pps film, polypropylene film, and np0 and x5r / x7r ceramics. lower grades than x5r or x7r are not recommended. the required values of cs can be noticeably affected by the presence and connection of the option resistors (see section 2.2). cs values should be adjusted for optimal sensitivity after the option resistors are connected. 3.4 power supply the power supply can range from 2.8 to 5.0 volts. if this fluctuates slowly with temperature, the device will track and compensate for these changes automatically with only minor changes in sensitivity. if the supply voltage drifts or shifts quickly, the drift compensation mechanism will not be able to keep up, causing sensitivity anomalies or false detections. the power supply should be locally regulated, using a three-terminal device, to between 2.8v and 5.0v. if the supply is shared with another electronic system, care should be taken to ensure that the supply is free of digital spikes, sags and surges which can cause adverse effects. it is not recommended to include a series inductor in the power supply to the qt1081. for proper operation a 0.1f or greater bypass capacitor must be used between vdd and vss; the bypass capacitor should be routed with very short tracks to the device?s vss and vdd pins. 3.5 pcb layout and construction refer to quantum application note an-kd02 for information related to layout and construction matters. l q 11 qt1081_1r0.04_0307
4 specifications 4.1 absolute maximum specifications operating temperature, ta ........................................................................................... -40c to +85 o c storage temp, ts .................................................................................................. -50 o c to +125 o c vdd................................................................................................................. -0.3 to +6.0v max continuous pin current, any control or drive pin ............................................................................ 20ma short circuit duration to ground or vdd, any pin ................................................................................ infinite voltage forced onto any pin ................................................................................... -0.3v (vdd + 0.3) volts 4.2 recommended operating conditions operating temperature, ta ............................................................................................ -40 o to +85 o c v dd ................................................................................................................. +2.8 to +5.0v short-term supply ripple+noise .............................................................................................. 5mv/s long-term supply stability .................................................................................................. 100mv cs range ............................................................................................................ 1nf to 100nf cx range ............................................................................................................... 0 to 50pf 4.3 ac specifications vdd = 5.0, ta = recommended, cx = 5pf, cs = 1nf; circuit of figure 1.1 end of touch ms 20 release time - all modes td r 180ms lp settin g ms 180 res p onse time - lp mode tdl ms 20 res p onse time - normal mode tdn ms 6 res p onse time - fast mode tdf both bursts to g ether ms 2.5 burst duration tbd ms 300 start-u p time from cold start tsu pulses appear 33 percent longer when viewed on an oscillosco p e. s 2 sample pulse duration tpc total deviation % 15 burst modulation , p ercent fm khz 132 burst center fre q uenc y fc ms 150 recalibration time trc notes units max typ min description parameter 4.4 dc specifications vdd = 5.0, ta = recommended, cx = 5pf, cs = 1nf; circuit of figure 1.1 unless noted bits 8 ac q uisition resolution a r a 1 in p ut leaka g e current i il 2.5ma source v vdd-0.5 hi g h out p ut volta g e v oh 7ma sink v 0.5 low out p ut volta g e v ol v 3.5 hi g h in p ut lo g ic level v hl v 0.7 low in p ut lo g ic level v il @ vdd = 2.8v v/s 100 avera g e su pp l y turn-on slo p e v dds @ vdd = 3.3v @ vdd = 2.8v a 15 10 average supply current, lp mode , ke y s on burst b onl y @ vdd = 3.3v; 340ms lp mode @ vdd = 2.8v ; 340ms lp mode a 22 15 average supply current, lp mode* i ddl @ vdd = 5.0 @ vdd = 4.0 @ vdd = 3.3 @ vdd = 2.8 ma 8 5.6 3.6 2.3 1.6 average supply current, normal mode* i ddn notes units max typ min description parameter *no spread spectrum circuit; rosc = 18k ? l q 12 qt1081_1r0.04_0307
4.5 signal processing vdd = 5.0, ta = recommended, cx = 5pf, cs = 1nf towards decreasin g cx load ms/level 500 anti-drift com p ensation rate towards increasin g cx load ms/level 2 , 000 normal drift com p ensation rate o p tion p in selected secs 10 , 60 , max on-duration must be consecutive or detection fails sam p les 2 detect inte g rator filter , ?fast? mode must be consecutive or detection fails sam p les 6 detect inte g rator filter , normal mode time to recalibrate if cx load has exceeded anti-detection threshold secs 2 anti-detection recalibration delay threshold for decrease of cx load counts 6 anti-detection threshold counts 2 detection h y steresis threshold for increase in cx load counts 10 detection threshold notes units value description l q 13 qt1081_1r0.04_0307
4.6 average idd curves all idd curves are average values, under the following conditions: cx = 5pf, ta = 20 o c, rosc = 18k ? ; no spread-spectrum circuit. refer to page 9 for more information about optimization of lp modes. full speed operation qt1081, average idd (full speed operation) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0123456 burst length (ms) idd (ma) vdd=5v vdd=4v vdd=3.3v vdd=2.8v low power operation (optimized - only burst b in use) qt1081, average idd (340ms optimized lp operation) 0.0 50.0 100.0 150.0 200.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v qt1081, average idd (180ms optimized lp operation) 0.0 100.0 200.0 300.0 400.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v qt1081, average idd (100ms optimized lp operation) 0.0 200.0 400.0 600.0 800.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v l q 14 qt1081_1r0.04_0307
low power operation (non-optimized) qt1081, average idd (340ms lp operation) 0.0 50.0 100.0 150.0 200.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v qt1081, average idd (180ms lp operation) 0.0 100.0 200.0 300.0 400.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v qt1081, average idd (100ms lp operation) 0.0 200.0 400.0 600.0 800.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v 4.7 lp mode typical response times l q 15 qt1081_1r0.04_0307 qt1081 response time (340ms lp operation) 290 310 330 350 370 390 410 430 2.5 3 3.5 4 4.5 5 5.5 vdd max. response time (ms) qt1081 response time (180ms lp operation) 160 170 180 190 200 210 220 230 240 2.5 3 3.5 4 4.5 5 5.5 vdd max. response time (ms) qt1081 response time (100ms lp operation) 90 95 100 105 110 115 120 125 130 2.5 3 3.5 4 4.5 5 5.5 vdd max. response time (ms)
4.8 mechanical - 32-qfn package symbol minimum nominal maximum a 0.70 - 0.95 a1 0.00 0.02 0.05 b 0.18 0.25 0.32 c - 0.20 ref - d 4.90 5.00 5.10 d2 3.05 - 3.65 e 4.90 5.00 5.10 e2 3.05 - 3.65 e-0.50- l 0.30 0.40 0.50 y 0.00 - 0.075 l1 0.00 - 0.10 dimensions in millimeters depending upon the ic assembly supplier, the package may be slightly different from that depicted above. see the magnified areas for the main difference between the ics. dimension l1 represents terminal pull-back from the package edge. where terminal pull-back exists, only the upper half of the lead is visible on the package edge due to half etching of the leadframe. the corner tie bar is connected internally to the exposed central pad. pin 1 exposed centre pad 0 . 4 3 m m corner tie bar note that there is no functional requirement for the large pad on the underside of this package to be soldered. if the final application requires this ar ea to be soldered for mechanical reasons, the pad to which it is soldered must be isolated and contained under the footprint only. l q 16 qt1081_1r0.04_0307
4.9 part marking 4.10 moisture sensitivity level (msl) ipc/jedec j-std-020c 260 o c msl3 specifications peak body temperature msl rating l q 17 qt1081_1r0.04_0307 yywwg run nr. ?yy? = year of manufacture ?ww? = week of manufacture ?g? = green/rohs compliant or ?xx? depending upon the ic assembly supplier pin 1 identification qrg revision code qt1081 ?qrg 1 qrg part no. 'run nr.' = 6 digit run number (depending upon the , this line may not appear) ic assembly supplier
5 datasheet control 5.1 changes changes this issue (datasheet rev 04) changes throughout to remove 48-ssop package. section 5: new. 5.2 numbering convention part number qt1081_mxn.nn_mmyy chip revision (where m= major chip revision, n = minor chip revision, x = prereleased product [or r = released product]) datasheet issue number datasheet release date; (where mm = month, yy = year) a minor chip revision (n) is defined as a revision change which does not affect product functionality or datasheet. the value of n is only stated for released parts (r). l q 18 qt1081_1r0.04_0307
notes: l q 19 qt1081_1r0.04_0307
l q copyright ? 2006-2007 qrg ltd. all rights reserved patented and patents pending corporate headquarters 1 mitchell point ensign way, hamble so31 4rf great britain tel: +44 (0)23 8056 5600 fax: +44 (0)23 8045 3939 www.qprox.com north america 651 holiday drive bldg. 5 / 300 pittsburgh, pa 15220 usa tel: 412-391-7367 fax: 412-291-1015 the specifications set out in this document are subject to change without notice. all produc ts sold and services supplied by qr g are subject to qrg?s terms and conditions of sale and services. qrg patents, trademarks and te rms and conditions can be found online at http://www.qprox.com /about/legal.php. numerous further patents are pending, one or more which may apply to this device or the a pplications thereof. qrg products are not suitable for medical (including lifesaving equipment) , safety or mission critical applications or other si milar purposes. except as expressly set out in qrg's te rms and conditions, no licenses to patents or other intellectual property of qrg (expres s or implied) are granted by qrg in connection with the sale of qrg products or provision of services. qrg w ill not be liable for customer pr oduct design and customers are entirely responsible for their products and applications which incorporate qrg's products. development team: john dubery, alan bowens, matthew trend

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